How ARM Processors Work: Storage, Endianness, and Memory Management

The ARM microprocessor, a 32-bit RISC architecture, is widely used in embedded systems due to its low power consumption and high efficiency. Its applications span mobile devices, industrial control, networking, and multimedia. ARM’s evolution, storage formats, and instruction sets, including RISC and Thumb technology, enhance its versatility and performance.

Catalog

What is an ARM microprocessor?

The ARM architecture, originally referred to as the Advanced RISC Machine and the Acorn RISC Machine, represents a 32-bit reduced instruction set (RISC) processor design. This architecture has gained significant traction in the realm of embedded system development, largely due to its remarkable low power consumption and exceptional energy efficiency. Such characteristics render it particularly suitable for mobile communication applications.

Examples of devices that leverage ARM processors include:

- Portable gadgets such as PDAs, mobile phones, multimedia players, and handheld electronic games.

- Computer peripherals, including hard drives and desktop routers.

- Military equipment, notably missile onboard computers.

The versatility of the ARM microprocessor allows it to adapt to various consumer electronics, enhancing user experience while maintaining a focus on sustainability and efficiency.

Application Field and Characteristics of ARM Microprocessor

ARM processors exhibit extensive market reach and a promising trajectory for development. Currently, ARM-based 32-bit microprocessors command 80% of the market share. Most IC manufacturers have developed proprietary ARM chips.

Industrial Control Applications:

ARM core-based microcontrollers, with their 32RISC architecture, dominate the high-end segment of the microcontroller market and increasingly permeate low-end applications. Their efficient energy use and favorable cost-performance ratio present a formidable challenge to traditional 8-bit and 16-bit microcontrollers.

Wireless Communication:

Currently, ARM technology is utilized in over 85% of wireless communication devices, reinforcing its standing in this sector through the offering of high performance at a lower cost.

Network Equipment:

With the advancement of broadband technology, ARM-based ADSL chips are gaining traction in competitive markets. Moreover, ARM's optimizations in voice and video processing receive substantial backing, challenging the DSP application field.

Consumer Electronics:

ARM technology underpins popular digital audio players, digital set-top boxes, and gaming consoles, steadily enriching the user experience.

Imaging and Security Products:

A significant number of digital cameras and printers incorporate ARM technology. Furthermore, the 32-bit SIM smart cards in phones leverage ARM technology.

ARM Processor Features:

- Compact design, power efficiency, cost-effectiveness, and robust performance

- Support for Thumb (16-bit) and ARM (32-bit) dual instruction sets, ensuring compatibility with 8-bit and 16-bit devices

- Abundance of registers facilitating rapid instruction execution

- Predominantly register-based data operations

- Flexible and straightforward addressing method contributing to operational efficiency

- Uniform instruction length

Delving into Core Concepts Surrounding ARM

Von Neumann System

Structural Model:

System Characteristics:

The synergy of data and instructions residing within a unified storage domain manifests a simplification that fuels many early computers. The dual use of a single data bus for fetching both instructions and data, despite its simplicity, presents a limitation. ARM7 utilizes this architecture, exemplifying simplicity intertwined with performance constraints, as concurrent data fetching remains elusive.

Harvard System

Structural Model:

Structural Features:

Distinct separation between program memory and data memory is observed, each harnessing its own bus to deliver expansive memory bandwidth, making it suitable for digital signal processing applications. This distinctiveness is prevalent in most DSPs which are designed based on Harvard architecture principles. ARM9, an embodiment of the Harvard architecture, elegantly divides memory into three categories: program, data, and shared program-data spaces, accommodating intricate computational needs.

Features of Complex Instruction Set Computer (CISC):

Encompassing a diverse array of instructions and addressing modes allows CISC architectures to offer extensive computational capabilities. A notable observation is the 8/2 rule, underscoring that typically 80% of program execution relies on merely 20% of available instructions. Although this extensive complement of instructions and circuitry culminates in powerful processing, it also results in increased spatial and power demands.

Reduced Instruction Set Computer (RISC)

Features:

Focused on implementing essential instructions that enable executing fundamental operations swiftly, RISC architecture facilitates expedited instruction execution by ensuring straightforward data operations. RISC adopts a load-store approach where the processor confines data handling to registers; specific load-store instructions orchestrate data interchange between registers and external storage. Streamlining the CPU design, RISC comprises fewer circuit units, yielding compactness and reduced energy consumption.

Distinguishing RISC and CISC Architectures

Register Usage:

The RISC instruction set boasts a plethora of versatile registers adept at holding both data and addresses, thereby enabling swift data access essential for efficient operations. Conversely, the CISC instruction set often employs registers for narrowly defined roles, limiting versatility.

Load-Store Structure:

RISC architecture champions a register-centric approach where exclusive load-store instructions oversee data transfer between registers and external memory, reducing the frequency of external memory access and optimizing stored data reuse. By contrast, CISC architecture allows direct memory data processing, offering flexibility at the cost of increased complexity.

ARM Storage Format

ARM storage is organized to hold data in 8-bit units, known as bytes, with each unit assigned a specific address.

ARM Memory Perspective

ARM interprets memory as a sequence of consecutive bytes commencing at zero address. It leverages its 32-bit microprocessor capability to offer an expansive addressing space reaching up to 4GB (2^32 bytes).

Data Arrangement in ARM Memory

The arrangement of stored data follows a specific pattern:

- The initial word data spans from zero to three bytes.

- The subsequent word data covers from the fourth byte to the seventh byte, sequentially.

The 32-bit word data occupies four address cells, whilst 16-bit half-word data uses up two address cells. Such distribution occasionally leads to complications concerning the sequence of storing word or half-word data.

Endianess in ARM Architecture

ARM architecture facilitates word data storage through two distinct methodologies: big-endian and little-endian formats.

Big-Endian Format

This format positions the high bytes of word data in lower address spaces, whereas the lower bytes of word data find themselves accommodated within higher address spaces.

Little-Endian Format

Conversely, in little-endian format, lower address spaces are utilized to store the low byte of the word data, while higher address spaces preserve the high byte of the word data. Generally, ARM defaults to small endian formatting.

ARM Architecture Insights

Exploration of ARM Series Products

Diverse Classification of ARM Processors

Instruction Set Architecture Classification:

- V1

- V2

- V5

- v5TEJ

- v6, and others

Processor Kernel Classification:

- ARM7

- ARM9

- ARM10

- ARM11

- Strong ARM

- XScale, among many others

Evolutionary Journey of ARM Architecture Versions

ARM architecture's journey has been a tapestry of technological advancement, marked by various versions:

- V1

- V2

- V3

- V4

- V5

- V6

Unveiling the V1 Architecture Version

The V1 architecture, reminiscent of a pioneering spirit, appeared solely in the ARM1 prototype, revealing its essence through key features:

- Fundamental data processing instructions (sans multiplication)

- LOAD/STORE instructions catering to bytes, half-words, and words

- Instructions for transfer, covering subroutine call and link

- Software interrupt handling instructions

- Addressing capacity: 64M bytes (26)

Exploration of the V2 Architecture Version

The V2 architecture, an enhancement of V1, as seen in ARM2 architecture, includes:

- Instructions for multiplication and advanced multiplication

- Co-processor operation instruction support

- Accelerated interrupt mode

- SWP/SWPB basic memory and register exchange instructions

- Addressing capacity: 64M bytes

Detailed Overview of the V3 Architecture Version

The V3 architecture presents expanded addressing, aiding in:

- Addressing space increased to 32 bits (4G bytes)

- Introduction of CPSR and SPSR registers for adept exception processing

- Abort and undefined processor modes added

- Embracing ARM6 utilization under this architecture

- Instruction set enhancements: MRS/MSR instructions accessing newly added CPSR/SPSR registers; exception handling return capability

Versatile Functions of the V4 Architecture Version

In the realm of V4 architecture, this version brings widespread application and further advancement over V3, encapsulating the essence of adaptability. ARM7, ARM8, ARM9, and Strong ARM incorporate this architecture.

New Instruction Set Features:

- Load/Store instructions for both signed and unsigned halfwords and signed bytes

- Introduction of the versatile 16-bit Thumb instruction set

- Enhanced SWI software interrupt instruction capabilities

- Inclusion of processor privilege mode

Cutting-edge Features in the V5 Architecture Version

The V5 architecture stands as a beacon of recent evolution, embedding new instructions from the V4 and propelling ARM10 and XScale applications. These advanced instructions include:

- BLX transfer instructions with linking and swapping features

- Leading zero count CLZ instruction

- BKPT software breakpoint instruction

- Additional signal processing instructions

- Expanded optional instructions for coprocessors

Vibrant Attributes of the V6 Architecture Version

The V6 architecture emerges as a fitting companion for battery-powered portable equipment, demonstrating thoughtful enhancements:

- SIMD function extension bolstering audio and video processing prowess within embedded systems.

Essential Guidelines for Selecting ARM Chips

In practical application scenarios, various factors shape the decision-making process when selecting ARM chips:

ARM Core Architecture

For those opting to use operating systems like WinCE or Linux to streamline software development timelines, selecting ARM chips equipped with MMU capabilities—such as those from the ARM720T and upwards—becomes advantageous.

System Clock Dynamics

The system clock intricately influences the ARM chip's processing velocity. ARM7 chips deliver speeds of 0.9 MIPS/MHz, with main clock frequencies stretching between 20 MIPS and 133MHz. By contrast, ARM9 chips offer enhanced speeds of 1.1 MIPS/MHz, with common clocks spanning from 100 MIPS up to 233MHz.

Intrinsic Memory Considerations

For scenarios devoid of the need for expansive memory, ARM chips equipped with internal memory present themselves as viable alternatives.

GPIO Usability Spectrum

Chip manufacturers often specify maximum GPIO capabilities, with numerous pins doubling as address, data, or serial lines. Consequently, evaluating the actual usable GPIO count becomes crucial during system design, revealing potential constraints and multifaceted applications.

USB Integration

Incorporating USB controllers, many ARM chips feature inbuilt capabilities; some even integrate both USB Host and USB Slave controllers, offering diverse interaction possibilities.

Interrupt Handling Mechanics

The fundamental ARM core design involves only two interrupt vectors: fast interrupt (FIQ) and standard interrupt (IRQ). Semiconductor developers augment chip designs with tailored interrupt controllers to accommodate hardware interrupts, spanning serial port, external triggers, and clock interruptions. Thoughtful external interrupt design can effectively mitigate task scheduling complexities, facilitating seamless operational flow.

LCD Display Integration

Certain ARM chips house intrinsic LCD controllers and can include advanced 64K color TFT LCD controllers. These are particularly suitable for PDA designs or handheld display and recording devices, ensuring vivid visual outputs tailored for specific user interactions.

Bus Expansion Versatility

Frequently, ARM chips include external interfaces for expanding SDRAM and SRAM. Variations in ARM chip designs determine the number of chips expandable via different pathways, influencing application breadth. Specific models, such as Micronas' PUC3030A, lack such external capabilities, mandating alternative architectural approaches.

Packaging Options

ARM chips come in varied packaging styles like QFP, TQFP, PQFP, LQFP, BGA, and LBGA. BGA packaging stands out for reducing chip dimensions and PCB area requirements, despite necessitating specialized welding technology beyond manual capabilities. Standard BGA-packed ARM chips further demand multi-layer PCB wiring, advancing beyond dual panel PCB interconnections.

Thumb Technology Insights

The evolution of ARM's RISC architecture offers innovative solutions characterized by remarkable power efficiency, condensed size, and enhanced performance. To address code length challenges, ARM architecture incorporates the T variant, pioneering a distinctive instruction system known as the Thumb instruction set.

Characteristics of Thumb

The Thumb instruction set, an extension of ARM, introduces 36 instruction formats derived from the traditional 32-bit ARM instruction set. These formats can be adaptively transformed into 16-bit opcodes, optimizing code density.

Processor State Versatility

ARM's architecture, capable of integrating Thumb support, allows seamless transitions to the Thumb state. Within this state, the processor engages with the 16-bit Thumb instruction set.

Thumb versus ARM: Comparative Analysis

Comparing the effectiveness of the ARM and Thumb instruction sets reveals notable distinctions. Thumb instructions typically demand additional processes to execute similar tasks, indicating ARM's suitability for time-sensitive applications.

In scenarios requiring exception handling, Thumb's instruction set lacks specific instructions. Consequently, ARM instructions must complement Thumb to manage exceptional interruptions efficiently. This emphasizes the synergistic relationship between Thumb and ARM instructions.

Frequently Asked Questions [FAQ]

1. What are the seven operating modes of an ARM microprocessor?

The ARM processor operates in multiple modes for specific tasks. User Mode (usr) runs applications, while FIQ and IRQ handle high-priority and standard interrupts. SVC manages OS resources, SYS executes privileged tasks, ABT handles data access errors, and UND manages unrecognized instructions. The CPU switches modes automatically or via software. Except for User Mode, all are privileged, with five—excluding SYS—classified as exception modes.

2. What are the basic addressing methods of an ARM microprocessor?

The ARM processor utilizes nine fundamental addressing modes, which determine the operand's location based on the address code specified in the instruction. These modes include register addressing, immediate addressing, register shift addressing, register indirect addressing, variable addressing, multi-register addressing, stack addressing, block copy addressing, and relative addressing. Each mode offers a distinct method for accessing data, enhancing the processor's flexibility and efficiency in executing tasks.

3. How many general-purpose registers does an ARM processor have?

The ARM microprocessor is equipped with a total of 37 registers, each 32 bits in size. Among these, 31 are designated as general-purpose registers. Notably, R13 and R13_svc are distinct from each other, ensuring that specific tasks can be managed effectively. Additionally, there are 6 state registers that play a crucial role in maintaining the processor's operational status.